A Hierarchical Simulation Framework for Application Development on System-on-chip Architectures

We propose a hierarchical simulation methodology to assist application development on System-on-Chip architectures. Hierarchical simulation involves simulation of a SoC based system at different levels of abstraction. Thus, it enables a system designer to exploit simulation speed vs. accuracy of results trade-offs. Vertical simulation is a special case of hierarchical simulation, where a feedback mechanism between the different simulation levels helps in “interpreting” the results of stand-alone simulations in the system-wide context. The paper presents an approach to perform vertical simulation of a class of applications under a simplfied scenario.